The present invention is directed to a memory constructed hierarchically of memory cells with pipeline registers. The memory hierarchically is constructed of memory cells, whereby the memory cells are combined into memory groups and column and row circuits for selecting, reading and writing every memory cell in the memory group, the memory being divided into lower, middle and higher hierarchy levels.
Static memories (SRAMs) in CMOS technology operate either asynchronously, i.e. a write or read event is triggered by a change in the input data, or synchronously with a clock. Registers are connected to an input and an output of the static memories. Input data can be address signals, data input signals, chip enable signals or other control signals. Controlling the input of data by means of a clock can be advantageous because the input data is accepted at a defined time with reference to a system clock and output data is also available at a defined time. This facilitates the data transfer between the modules of a system operating at a predetermined frequency. Based on these considerations, synchronous static memories were developed, which are referred to as "registered SRAMs" or "pipelined SRAMs". Such synchronous SRAMs may be found in the publication, GaAs IC Data book and Designer's Guide, "256.times.4 Bit Registered Self-Timed Static RAM 2.5 ns Cycle Time", Giga Bit Logi Inc., May, 1988, page 2--2, as well as in the publication, CMOS Data Book, "Advanced Information: Self-Timed Pipeline Static RAMs" , Cypress Semiconductors, Jan. 15, 1988, page 2-83. The static memories shown therein, however, contain only pipeline registers at their inputs and outputs.
In addition to the synchronization, it is a goal of pipeline architecture to provide an optimally high clock frequency for the operation of a circuit. This is achieved by dividing the data path into a plurality of sections that are operated in parallel clock-controlled chronologically for a plurality of data sets. After passing through a pipeline stage, the data are intermediately stored in registers. The shortest possible clock period is thereby defined by the pipeline stage or by the pipeline stages having the longest transit time. The overall running time of the data through this circuit is longer than the running time for a circuit without a pipeline structure. However, depending on the number of pipeline stages and the additional running time through the registers, the data rate can be significantly increased. This advantage is achieved at the expense of an additional area requirement for the pipeline registers as well as the generation and distribution of the clock signals.
A subdivision of the read or write event into further pipeline stages is not meaningful with conventional memory architecture without hierarchic stages. Following a pre-decoder stage that makes use of only a small part of the access time, the input signals can be branched to a plurality of word lines. Due to the great plurality of word lines, the drive levels required for the word line signal and the geometry parameters due to the cell grid, it is not meaningful to insert further pipeline registers into the address path at this location. The output data are selected from a plurality of data lines and are supplied to one or more read amplifiers. An intermediate storage is only meaningful following the read amplifier.